1. Field of the Invention
The present invention relates to substrate biasing of semiconductor devices to reduce sub-threshold leakage, and more particularly to a system and method for adjusting supply voltage levels to reduce sub-threshold leakage.
2. Description of the Related Art
Complementary Metal-Oxide Semiconductor (CMOS) circuitry dissipates less power and is more dense than other types of integrated circuit (IC) technologies so that CMOS technology has become the dominant style of digital circuit design for integrated circuits. CMOS circuits use a combination of N channel (NMOS) and P channel (PMOS) devices each having a threshold gate-to-source voltage based on design, scale, materials and process. As IC design and fabrication techniques continue to evolve, operating voltages and device sizes have each scaled downward. The 65 nanometer (65 nm) process is an advanced lithographic process used for volume CMOS semiconductor fabrication and is particularly advantageous for Very Large Scale Integrated (VLSI) circuits, such as microprocessors and the like. As device sizes and voltage levels have decreased, the channel lengths and oxide thicknesses of each device have also decreased. Manufacturers have also switched to gate materials causing lower voltage thresholds which has further led to increased sub-threshold leakage current. Sub-threshold leakage current is the current that flows between the drain and source when the gate-to-source voltage is below the threshold voltage of the CMOS device. In many conventional circuits the substrate interface of each CMOS device, also referred to as the well or bulk tie, is coupled to a corresponding one of the supply voltage rails (e.g., PMOS bulk tied to VDD and NMOS bulk tied to VSS). In such conventional configurations the sub-threshold leakage current may account for nearly 30% or more of total power consumption in the dynamic environment (e.g., during normal operation).
It is often desired to operate an IC in a lower power mode (e.g., sleep or hibernation mode) and reduce power consumption as much as possible. As one skilled in the art will appreciate, increasing the threshold voltage of a CMOS device results in decreased leakage current. And since threshold voltage is proportional to the square root of the value of the drain-to-source voltage of the device, an increase in this drain-to-source voltage results in an increase in threshold voltage, thus resulting in a lower leakage current. Accordingly, in certain configurations a bias generator or charge pump is provided on the chip die and is used to bias device substrates to a voltage level other than the power supply voltages during low power mode. In particular, the charge pump raises the bulk tie of PMOS devices above VDD and lowers the voltage of the bulk tie of NMOS devices below VSS. Such substrate biasing significantly reduces the sub-threshold leakage current during low power mode thereby conserving a substantial amount of power. Charge pump circuits or the like are typically used to increase the substrate (bulk tie) voltage of P-channel devices above the positive supply voltage and to reduce the substrate voltage of N-channel devices below the negative supply voltage. The charge pump solution, however, presents certain inefficiencies by increasing the overall voltage range beyond the supply voltage range between VDD and VSS.